Generally in computer systems and especially in personal computer systems, data is transferred between various system devices such as the central processing unit (CPU), memory devices, and direct memory access (DMA) controllers. In addition, data may be transferred between expansion elements such as input/output (I/O) devices, and between these I/O devices and the various system devices. The I/O devices communicate with the system devices and amongst each other over computer buses, which comprise a series of conductors along which information is transmitted from any of several sources to any of several destinations. Many of the system devices and the I/O devices are capable of serving as bus masters which can control operations occurring over the computer bus.
Personal computer systems typically are architected in a single bus or dual bus configuration. In a dual bus system, bus masters may operate simultaneously on both buses. In a single bus configuration, however, only one bus master may control the system bus at a given instant in time, because simultaneous activity on the bus is prohibited. Accordingly, efficient use of the system bus by both system devices and I/O devices is an important consideration in the overall system design.
During normal operation of a single bus computer system, both the CPU and the various I/O devices capable of operating as bus masters compete for control of the single system bus. Typically, DMA channels handle arbitration between the CPU and the various I/O devices. Once a bus master obtains control of the bus, however, the time during which it can maintain exclusive control of the bus is not limited. Thus, the bus master currently in control of the bus has no way of determining whether it may retain control of the bus or whether it should relinquish control of the bus. As a result, system performance may be diminished by inefficient control of the bus.
For some system devices, if a system bus control request is not granted within a specific time period, data underruns and overruns may occur. Thus, data may be lost if a bus control request by a second I/O device is ignored while a first I/O device maintains control of the bus to perform a time consuming operation. To complicate matters further, bus control request lines are often able to float to a high logic level, thereby erroneously indicating that the second I/O device has requested access to the system bus when it actually has not.
It is an object of the present invention, then, to provide preemption control logic which recognizes system bus control requests made by a second bus master device while a first bus master device is in control of the bus, and prompts the first bus master device to relinquish control of the bus to the second bus master device, thereby insuring efficient and effective data transfer over the system bus. It is a further object of the present invention to prevent erroneous signals indicating that an I/O device has requested control of the system bus.